ngVLA Enabling Technologies


Integrated Receiver Development

The Integrated Receiver Development (IRD) program is an ongoing effort to develop modern integrated receiver architectures for radio astronomy that digitize early and are easier to manufacture and maintain in large numbers compared to conventional assemblies. A wide range of novel technologies has been developed, patented, and licensed in order to make these advancements possible.

At the core of this program is the idea that modern integrated electronics and digital signal processing (DSP) are complementary to each other. Numerical signal processing is capable of providing a level of flexibility and precision that is unachievable using purely analog means, while integrated technology provides the stable calibrations and smooth spectral baselines that are needed for the DSP to realize its full potential.

Each module is designed to immediately follow the cryogenic gain stage, and comprises everything that remains in the signal path operating at room temperature inside the antenna. This means that all conversions from RF-to-baseband, from analog-to-digital, and from copper-to-fiber are combined into a single, compact unit. Unique, multi-technology packaging and assembly techniques assure the best performance from micro-scale electronics with excellent digital-to-analog and channel-to-channel isolation.

The intrinsic receiver architecture is that of a single-stage, I/Q downconversion, using just one LO to get from the sky-frequency to baseband for immediate digitization. This allows for the earliest possible digitization in high-frequency systems while minimizing the potential for LO spurs and maximizing the instantaneous bandwidth for a given sample rate. Final separation of the I- and Q-channels into sidebands is deferred to the digital back-end for precise image-rejection, typically in excess of 50 dB, and is extremely stable over both time and temperature.

Integrated fiber-optic transceivers launch the raw, digital, I and Q data onto single-mode fibers with ranges of several meters to tens of kilometers. A unique, power-efficient, resolution-agnostic ADC-Serializer is under development which will further reduce power consumption. This will be supported in the back-end by a firmware IP block that can be installed on an FPGA platform and parses the data stream according to a novel, patent-protected algorithm. In this way, all the advantages of digital data transmission can be realized without most of the digital overhead normally required at the transmitter, such as bit-scrambling, packetizing, and framing.

While fabrication techniques vary by band, the overall concepts described above apply readily to the entire ngVLA frequency range. The most significant benefits of early digitization and the high level of stability afforded by these modules include reliability and scalability.


SERIAL ADC 

  • Current Demo Sample Rate:
    • up to 1 GS/s @ 8 bits resolution 
  • Future Planned Sample Rates:
    • 4 GS/s @ 14 bits resolution
    • 7 GS/s @ 8 bits resolution
    • 14 GS/s @ 4 bits resolution

RF INPUT Bands:

  • 1.2 - 3.5 GHz
  • 3.5 - 12. 3 GHz
  • 12.3 - 20.5 GHz
  • 20.5 - 34 GHz
  • 30.5 - 50.5 GHz
  • 70 - 116 GHz

COMPACT PACKAGE:

  • est. 1.5 x 3 x 6 inches per band (dual-polarization)

I/Q FIBER OUTPUT:

  • 1310 nm, single-mode
  • Current Serial Rate:
    • 8 Gbps (NRZ)
  • Future Planned Serial Rates:
    • 28 Gbps (NRZ)
    • 56 Gbps (PAM4)

 

Integrated Receiver Schematic

Exploded view of W-band prototype.


 


 

 

IRD Block Diagram

Internal block diagram of a compact analog-digital-photonic receiver.

 


 

 

Integrated Receiver 2

S-Band prototype integrated receiver.